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HANBit
HDD32M64F8
DDR SDRAM Module 256Mbyte (32Mx64bit), based on 32Mx8, 4Banks, 8K Ref., SMM, Part No. HDD32M64F8
GENERAL DESCRIPTION
The HANBiT HDD32M64F8 is 32M bit x 64 Double Data Rate SDRAM high density memory modules. The HANBiT HDD32M64F8 consists of eight CMOS 32M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 200pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD32M64F8 is Dual In-line Memory Modules and inten-ded for mounting into 200pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
FEATURES
* Part Identification
HDD32M64F8 - 10A HDD32M64F8 - 13A HDD32M64F8 - 13B : 100MHz (CL=2) : 133MHz (CL=2) : 133MHz (CL=2.5)
* Power supply : VDD: 2.5V 0.2V, VDDQ: 2.5V 0.2V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe(DQS) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency 2, 2.5 (clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM
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PIN ASSIGNMENT
P1 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol /CS0 NC VSS CKE0 NC NC VDD CK0 CK1 NC VSS NC DM0 DM4 VDDQ NC NC VSS NC DQS0 DQS4 VDD NC DQ0 DQ1 VSS DQ2 DQ3 VDDQ DQ4 DQ5 DQ6 VSS DQ7 PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Symbol DQ15 DQ14 VDDQ DQ13 DQ12 DQ11 VSS DQ10 DQ9 DQ8 VDD *SA0 *SA1 VSS *SA2 VDDQ VDD /RAS VSS /CAS /CK0 /CK1 VDD /CK2 CK2 /WE VSS NC DM1 DM5 VDDQ NC VREF VSS PIN 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Symbol NC DQS1 DQS5 VDD NC DQ39 DQ38 VSS DQ37 DQ36 VDDQ DQ35 DQ34 DQ33 VSS DQ32 DQ40 DQ41 VDDQ DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 *SCL *WP *VSPD VSS *SDA VDDIN PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol VDDQ A3 VSS A2 A1 A0 VDD A10 A11 BA0 VSS BA1 DM2 DM6 VDDQ NC NC VSS DQS7 DQS2 NC VDD DQ31 DQ30 DQ29 VSS DQ28 DQ27 VDDQ DQ26 DQ25 DQ24 VSS DQ16 PIN 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 P2
HDD32M64F8
Symbol DQ17 DQ18 VDDQ DQ19 DQ20 DQ21 VSS DQ22 DQ23 NC(CB6) VDD NC(CB4) NC(CB2) VSS NC(CB0) VDDQ VDD A4 VSS A5 A6 A7 VDD A8 A9 A12 VSS DM3 DM7 NC(DM8) VDDQ NC NC(A13) VSS
PIN 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol NC(DQS8) DQS3 DQS6 VDD DQ56 DQ57 DQ58 VSS DQ59 DQ60 VDDQ DQ61 DQ62 DQ63 VSS DQ55 DQ54 DQ53 VDDQ DQ52 DQ51 DQ50 VSS DQ49 DQ48 NC(CB7) VDD NC(CB5) NC(CB3) VSS NC(CB1) VDD
* These pins should be NC in the system which does not support SPD PIN A0~A12 BA0~BA1 DQ0~DQ63 CB0~CB7 DQS0~DQS7 DM0~DM7 CK0~CK2,/CK0~/CK2 CKE0 /CS0 /RAS /CAS
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PIN DESCRIPTION Address input Bank Select Address Data input/output Check bit(Data input/output) Data Strobe input/output Data-in Mask Clock input Clock enable input Chip Select input Row Address strobe Column Address strobe
2
PIN VDD VDDQ VREF VSPD VSS SA0~SA2 SDA SCL WP VDDIN NC
PIN DESCRIPTION Power supply(2.5V) Power supply for DQs(2.5V) Power supply for reference Serial EEPROM Power supply(3.3) Ground Address in EEPROM Serial data I/O Serial clock Write protection VDD indentification flag No connection
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FUNCTIONAL BLOCK DIAGRAM
HDD32M64F8
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PIN FUNCTION DESCRIPTION
Pin CK, /CK Clock Name
HDD32M64F8
Input Function CK and /CK are differential clock inputs. All address and control input signals are sampled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK. CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE
CKE
Clock Enable
POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled during power-down and self refresh modes, providing low standby power. CKE will recognizean LVCMOS LOW level prior to VREF being stable on power-up. /CS enables(registered LOW) and disables(registered HIGH) the command decoder.
/CS
Chip Select
All commands are masked when /CS is registered HIGH. /CS provides for external bank selection on systems with multiple banks. /CS is considered part of the command code. Row/column addresses are multiplexed on the same pins.
A0 ~ A12
Address
Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE
BA0 ~ BA1
Bank select address
command is being applied. Latches row addresses on the positive going edge of the CLK with /RAS low.
/RAS
Row address strobe
Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with /CAS low.
/CAS
Columnaddress strobe
Enables column access. Enables write operation and row precharge.
/WE
Write enable
Latches data in starting from /CAS, /WE active. Output with read data, input with write data. Edge-aligned with read data, cen-
DQS0 ~ 7
Data Strobe
tered in write data. Used to capture write data. DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled
DM0~7
Input Data Mask
on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS load-ing.
DQ0 ~ 63
Data input/output
Data inputs/outputs are multiplexed on the same pins. WP pin is connected to Vcc.
WP
Write Protection
When WP is "high" EEPROM Programming will be inhibited and the entire , memory will be write-protected.
VDDQ VDD VSS VREF
Supply Supply Supply Supply
DQ Power Supply : +2.5V 0.2V. Power Supply : +2.5V 0.2V (device specific). DQ Ground. SSTL_2 reference voltage.
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ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Voltage on VDDQ supply relative to Vss Storage temperature Power dissipation SYMBOL VIN, VOUT VDD VDDQ TSTG PD RATING -0.5 ~ 3.6 -1.0 ~ 3.6 -0.5 ~ 3.6 -55 ~ +150 8.0
HDD32M64F8
UNTE V V V C W mA
Short circuit current IOS 50 Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
POWER & DC OPERATING CONDITIONS
(Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70 ) C)
PARAMETER Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage(system) Input High Voltage Input Low Voltage Input Voltage Level, CK and /CK inputs Input Differential Voltage, CK and /CK inputs Input leakage current Output leakage current Output High current (VOUT = 1.95V) Output Low current (VOUT = 0.35V) Output High Current(Half strengh driver) Output High Current(Half strengh driver) SYMBOL VDD VDDQ VREF VTT VIH (DC) VIL (DC) VIN (DC) VID (DC) I LI I OZ I OH I OL IOH IOL MIN 2.3 2.3
VDDQ/2-50mV
MAX 2.7 2.7
VDDQ/2+50mV
UNIT V V V V V V V V uA uA mA mA mA mA
NOTE
1 2
VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.3 -2 -5 -16.8 16.8 -9 9
VREF + 0.04 VREF + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 2 5
3
Notes 1. Includes 25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards.
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INPUT/OUTPUT CAPACITANCE
DESCRIPTION
HDD32M64F8
(VDD = 2.5V, VDDQ = 2.5V, TA = 25 f = 1MHz) C,
SYMBOL MIN MAX UNITS
Input Capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE ) Input Capacitance(CKE0) Input Capacitance( CS0) Input Capacitance( CLK0, CLK1,CLK2 ) Data & DQS input/output Capacitance(DQ0~DQ63) Input Capacitance(DM0~DM8)
CIN1 CIN2 CIN3 CIN4 COUT1 CIN5
49 42 42 22 6 6
57 50 50 25 8 8
pF pF pF pF pF pF
AC OPERATING CONDITIONS
PARAMETER/ CONDITION STMBOL MIN MAX UNIT NOTE
Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs
VIH (AC) VIL (AC) VID (AC) VIX (AC)
VREF + 0.31 VREF - 0.31 0.7 0.5*VDDQ-0.2 VDDQ+0.6 0.5*VDDQ+0.2 V V V
3 3 1 2
Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a VREF envelope that has been bandwidth limited 20MHz.
AC OPERATING TEST CONDITIONS
PARAMETER Input reference voltage for Clock Input signal maximum peak swing Input signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition VALUE 0.5 * VDDQ 1.5 0.5 VREF+0.31/VREF-0.31 VREF VTT See Load Circuit UNIT V V V/ns V V V V NOTE
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DDR200 PARAMETER SYMBOL -10A MIN MAX MIN DDR266A -13A MAX
HDD32M64F8
DDR266B -13B MIN MAX UNIT NOTE
AC TIMMING PARAMETERS & SPECIFICATIONS (THESEACCHARICTERISTICSWERETESTEDON THECOMPONENT)
Row cycle time Refresh row cycle time Row active time /RAS to /CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command Col. address to Col. address delay CL=2.0 Clock cycle time CL=2.5 Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble Data out high impedence time from CK-/CK CK to valid DQS-in DQS-in setup time DQS-in hold time DQS-in falling edge to CK rising-setup time DQS-in falling edge to CK rising hold time DQS-in high level width DQS-in low level width DQS-in cycle time Address and Control Input setup time Address and Control Input hold time Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS DQ & DM input pulse width Power down exit time
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tRC tRFC tRAS tRCD tRP tRRD tWR tCDLR tCCD tCK
70 80 48 20 20 15 2 1 1 10 12 12 120K
65 75 45 20 20 15 2 1 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.2 0.2 0.35 0.35 1.1 0.9 0.9 0.9 15 0.5 0.5 1.75 10 1.1 12 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25 120K
65 75 45 20 20 15 2 1 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 -0.75 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 0.9 15 0.5 0.5 1.75 10 1.1 12 12 0.55 0.55 +0.75 +0.75 +0.5 1.1 0.6 +0.75 1.25 120K
ns ns ns ns ns ns tCK tCK tCK ns ns tCK tCK ns ns ns tCK tCK ns tCK ns tCK tCK tCK tCK tCK tCK ns ns ns ns ns ns ns
1 1,2 1,2 3 3 3 3 2
tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tHZQ tDQSS tWPRES tWPREH tDSS tDSH tDQSH tDQSL tDSC tIS tIH tMRD tDS tDH tDIPW tPDEX
0.45 0.45 -0.8 -0.8 0.9 0.4 -0.8 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 1.1 1.1 16 0.6 0.6 2 10
7
0.55 0.55 +0.8 +0.8 +0.6 1.1 0.6 +0.8 1.25
2
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Exit self refresh to write command Exit self refresh to bank active command Exit self refresh to read command Refresh interval time Output DQS valid window DQS write postamble time Notes : tXSW tXSA tXSR tREF tQH tWPST 116 80 200 15.6 0.35 0.25 95 75 200 15.6 0.35 0.25
HDD32M64F8
ns 75 200 15.6 0.35 0.25 ns Cycle us tCK tCK 4 1
1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are 45% of the period including both the half period jitter (tJIT(HP) ) of the PLL and the half jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate tIS (V/ns) (ps) 0.5 0 0.4 +50 0.3 +100 tIH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate tIS (V/ns) (ps) 0.5 0 0.4 +75 0.3 +150 tIH (ps) 0 +75 +150
This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level tDS (mV) (ps) +50 280 tDH (ps) +50
This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate tDS (ns/V) (ps) 0 0 0.25 +50 0.5 +100 tDH (ps) 0 +50 +100
This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time.
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CKE n-1 CKE n BA 0,1
HDD32M64F8
A10/ AP A11 A9~A0
COMMAND TRUTH TABLE (V=VALID, X=DO T CARE, H=LOGIC HIGH, L=LOGIC LOW)
COMMAND /CS /RAS /CAS /WE DM NOTE
Register Register
Extended MRS Mode register set Auto refresh Entry Exit
H H H L H
X X H L H X
L L L L H L
L L L H X L
L L L H X H
L L H H X H
X X X X X V
OP code OP code X X Row address L Column Address H (A0 ~ A9) Column Address H (A0 ~ A9) X V X L H X X
1,2 1,2 3 3 3 3
Refresh
Self refresh
Bank active & Row Addr. Read & column address Write & column address Burst Stop Precharge Bank selection All banks Entry Exit Entry Exit Auto disable Auto eable Auto disable Auto enable precharge precharge precharge precharge
4 4 4 4,6 7 5
H
X
L
H
L
H
X
V
H H X L H L L H H H L H L H H X H L X X L H L H L L H L X H L H L H L X V X X H X V X X H X H X H H H X V X X H X V L L X V X X H X V X X X X X X V
L
Clock suspend or active power down
Precharge power down mode DM
X X V X X X 8
No operation command Note :
1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
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PACKAGE DIMENSIONS
Unit : mm
HDD32M64F8
Front - Side
Rear-Side
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ORDERING INFORMATION
HDD32M64F8
Part Number
Density
Org.
Package
Ref.
Vcc
MODE
MAX.frq
HDD32M64F8-10A HDD32M64F8-13A HDD32M64F8-13B
256MByte 256MByte 256MByte
32M x 64 32M x 64 32M x 64
200PIN SMM 200PIN SMM 200PIN SMM
8K 8K 8K
2.5V 2.5V 2.5V
DDR DDR DDR
100MHz/CL2 133MHz/CL2 133MHz/CL2.5
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